Overview of the ESP32-S31 Features

A walkthrough of the ESP32-S31 features

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This lecture covers the ESP32-S31 and the ESP32-S31-Function-CoreBoard-1 before you enable Secure Boot, flash encryption, and the other assignment modules. The SoC offers dual RISC-V cores with Wi-Fi 6, Bluetooth 5.4, IEEE 802.15.4, a Gigabit Ethernet MAC, and security hardware documented in the datasheet and ESP-IDF documentation.

This is a walkthrough, not a TRM chapter. You will see which peripherals matter on the bench, which security blocks the security overview configures, how the ESP32-S31-Function-CoreBoard-1 exposes USB and Ethernet for the labs, and where to open the official docs when you need pin names, etc. The introduction describes how that path fits the rest of the workshop.

Learning objectives

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By the end of this lecture, you should be able to:

• Name the main ESP32-S31 wired and multimedia peripherals compared with earlier ESP32 parts
• List the SoC security blocks that the later assignments use
• Point to the ESP32-S31-Function-CoreBoard-1 connectors used to flash, debug, and run TLS labs
• Choose the right Espressif datasheet, TRM, board guide, or ESP-IDF security page for a given question

System and connectivity

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The ESP32-S31 has a dual-core 32-bit RISC-V CPU at up to 320 MHz, 512 KB internal SRAM, and external PSRAM and flash over high-speed SPI. One core implements 128-bit SIMD for signal-processing style workloads. An MMU maps external memory, which you rely on once flash encryption is enabled and the application grows.

For radios and wired links, the SoC integrates 2.4 GHz Wi-Fi 6 (802.11ax), Bluetooth 5.4 (LE and Classic), IEEE 802.15.4 (Thread and Zigbee), and a Gigabit Ethernet MAC. On the ESP32-S31-Function-CoreBoard-1, the RJ45 port is an easy choice for TLS when you want a fixed wired lab network instead of Wi-Fi credentials in a classroom.

New peripherals on the ESP32-S31

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If you have used ESP32-S3 or ESP32-C SoCs, the I/O list will look familiar but longer. The ESP32-S31 has 60 programmable GPIOs, multiple UART/SPI/I2C blocks (including low-power variants), USB 2.0 High-Speed OTG, USB Serial/JTAG, TWAI (CAN FD), SDIO, timers, ADCs, touch sensing, and motor-control PWM.

For display and audio products, the same SoC adds a JPEG codec, Pixel Processing Accelerator (PPA), 2D-DMA, camera and LCD controllers, and I2S with hardware Bluetooth audio timing. The security assignments ignore most of that, but it matches the ESP32-S31-Function-CoreBoard-1 layout: Ethernet, USB host, microphone, and speaker for connected voice demos.

The table below ties SoC interfaces to this workshop:

Security elements (overview)

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The security features overview covers these blocks in detail. The ESP32-S31 includes a cryptography and security component described in the ESP-IDF security overview:

• Secure Boot and flash/PSRAM encryption for authenticity and confidentiality of code and data at rest
• Hardware accelerators (AES, SHA, RSA, ECC, HMAC) and a True Random Number Generator (TRNG) for TLS and provisioning
• Digital signature peripherals (RSA_DS, ECDSA_DS) so private signing material can stay out of normal software reach
• Secure Debug Controller, power-glitch detection, and side-channel hardening on selected blocks
• Access Permission Management (APM) and Trusted Execution Environment (TEE) support for isolating software on multi-app products

The assignments enable these controls one module at a time.

Development kit: ESP32-S31-Function-CoreBoard-1

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The ESP32-S31-Function-CoreBoard-1 is the board used in this workshop. It carries the ESP32-S31-WROOM-3 module (16 MB flash and 16 MB PSRAM in the mass-production configuration), breaks out GPIOs on header J2, and adds Gigabit Ethernet, two USB-C ports (UART bridge and native USB Serial/JTAG), a USB 2.0 Type-A host port, microphone and speaker paths through an ES8311 codec, an addressable RGB LED, and Boot and Reset buttons.

Power the board from either USB-C port or the 5 V and GND pins on J2. For daily ESP-IDF work, the USB Serial/JTAG port is enough to build, flash, and monitor; the USB-to-UART port is a familiar fallback. Use Ethernet when you want TLS on a fixed lab network.

Block diagram

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The diagram below shows how the ESP32-S31-WROOM-3 module connects to USB, Ethernet, and audio on the board.

Board components

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The front of the board contains the interfaces and controls used most often during development:

The back of the board contains additional interface circuitry:

Software support

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Use ESP-IDF v6.1 with target esp32s31, as listed in the workshop prerequisites. Install and activate the framework with EIM or the ESP-IDF extension for VS Code, then open or create a project and run idf.py --preview set-target esp32s31.

Espressif also publishes esp_board_manager for the ESP32-S31-Function-CoreBoard-1, which can initialize the codec, LED, and buttons when you move past bare security examples. Secure boot, encryption, and related options still come from ESP-IDF Kconfig, eFuse, and the guides in the next section.

Documentation and resources

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Use these references while you work through the workshop:

For a first flash and serial connection, follow ESP-IDF Get Started for ESP32-S31.

Navigation

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Next: Overview of the security features on the ESP32-S31

Return to the workshop main page